The present invention relates generally to power factor correction (PFC) circuits for alternating current (AC) to direct current (DC) power converters. More particularly, this invention pertains to stabilizing operation of a PFC circuit of an AC to DC converter for a wide range of operating conditions.
Referring to FIG. 1, an AC to DC power converter 100 includes a simple multiplier circuit 102 as part of a PFC circuit 104. Typically, the control loop for a critical conduction mode PFC circuit 104 can be optimized easily if the input voltage has a maximum up to triple the minimum of the input voltage as long as the output power of the PFC circuit 104 is fixed. When the input power (i.e., input voltage and input current product) changes dramatically, for example, from 110 w to 5 w, the PFC circuit 104 tends to lack stability at high input voltage and low input current. Control loop gain is determinative of control loop stability for the PFC circuit 104. PFC circuit multiplier gain is a factor in this loop gain. Equation 1 shows a general transfer function between control to output for a PFC circuit block.Gc_o(s)=Kp×G1(s)  EQUATION 1:
In Equation 1, KP is the multiplier gain which is defined by (R2*Vin)/R1. G1(s) is the open loop control to output transfer function without multiplier gain. Gc_o(s) is the open loop input to output transfer function accounting for the multiplier gain. Generally, the higher the gain, the less stable a control loop will be.
In the prior art PFC circuit 104 of FIG. 1, the PFC circuit 104 further includes a controller 106 having a multiplier voltage input 108. The controller 106 determines the multiplier gain (i.e., loop gain) as a function of the voltage at the multiplier voltage input 108. The conventional simple multiplier circuit 102 provides the multiplier voltage via a resistive divider formed by resistors R1 and R2. The multiplier voltage thus changes in direct proportion to the input voltage. The multiplier is relatively low when input voltage Vin is relatively low and relatively high when the input voltage Vin to the PFC circuit 104 is relatively high.
When the input power is relatively low and the input voltage Vin is relatively high, the multiplier circuit 102 cannot meet the stability requirement, i.e., the multiplier or gain is higher when it needs to be lower at high input voltage Vin. An ideal multiplier circuit design should provide a lower voltage to the multiplier voltage input 108 of the controller 106 when input voltage Vin increases and input power decreases (i.e., input current decreases) to maintain stability over an increased range of operating conditions.